A nonvolatile memory is a type of memory that retains stored data when power is removed. There are various types of nonvolatile memories, including read only memories (ROMs), programmable read only memories (PROMs), erasable programmable read only memories (EPROMs), and electrically erasable programmable read only memories (EEPROMs). EEPROMs and flash EEPROMs are commonly used in data processing systems requiring a nonvolatile memory that is reprogrammable.
A flash EEPROM generally includes an array of floating gate, single transistor memory cells. As with an EPROM, the entire memory array of a flash EEPROM is bulk erased, but instead of using ultraviolet (UV) light to erase the cells, an electrical signal is used. The term "flash" refers to the fact that the flash EEPROM can be erased much more quickly than an EPROM. It may take less than two minutes to erase a flash EEPROM memory cell, compared to about 20 minutes to erase an EPROM with UV light.
Once the flash EEPROM is bulk erased, Selected cells are programmed using various methods. A programmed flash EEPROM cell provides a logical one when programmed and an unprogrammed flash EEPROM cell provides a logical zero. A cell may be programmed by applying a high programming voltage to the control gate, and a power supply, voltage to the drain with the source grounded. Hot carrier injection causes electrons to be transported from the source region to the floating gate and become trapped since the floating gate is isolated from the control gate by an interpoly dielectric layer and from the drain-source region by a thin oxide layer. The effect of trapping electrons on the floating gate is to raise the floating gate transistor's threshold voltage (V.sub.T). The raised V.sub.T prevents the transistor from becoming conductive to the array ground at normal read cycle voltages, thereby providing a logic one that is sensed by a sense amplifier when read. The non-programmed transistors have a lower V.sub.T and become conductive to the array ground at normal read cycle voltages and provide a logic zero when read. Because the floating gate is isolated, the cell can remain programmed or erased for an extended period of time (10 years or longer).
To erase the array of floating gate transistors, a high positive voltage is applied between the source and the control gate of each transistor. Electrons are transported from the floating gate to the source region by Fowler-Nordheim tunneling. Removal of the electrons from the floating gate has the effect of lowering the V.sub.T of the floating gate transistor If the high positive voltage is applied for too long, some of the floating gate transistors may be over-erased. A floating gate transistor is over-erased when the V.sub.T of the transistor becomes negative. A floating gate transistor normally functions like an enhancement mode device, however with a negative V.sub.T the floating gate transistor functions like a depletion mode device. When the floating gate transistor operates in depletion mode, it stays at least partially conductive, even when not selected, and may prevent the cells on the same bit line from being correctly read, leading to failure of the entire memory. U.S. Pat. No. 5,130,769, "Nonvolatile Memory Cell", issued to Kuo et al. on Jul. 14, 1992, describes a prior art flash EEPROM cell (FIG. 1 and FIG. 2) that is susceptible to over-erasure.
Because of variations in process and erase timing, the flash EEPROM cells may not erase at the same rate. Therefore, the floating gate threshold voltages may differ by 2 volts or more after aft erase operation. A wide distribution of threshold voltages reduces margins and limits the ability of the flash EEPROM array to function properly and reliably at low power supply voltages, such as 3 volts.
Several techniques have been developed to correct, and to prevent, over erasure of flash EEPROM cells and to converge the V.sub.T distribution of the floating gate transistors within a predetermined voltage range. One common technique used to prevent over-erasure is known as intelligent erase. To perform an intelligent erase, all of the flash EEPROM cells of the array are first programmed. Then, the cells are gradually erased in steps using an erase pulse of relatively short duration. After the application of each erase pulse, a verification step is used to check the V.sub.T to determine if the V.sub.T has been sufficiently reduced. The erase and verify steps are repeated until none of the cells register a programmed response to the verification step. This technique is generally effective, however it is time consuming and adds complexity to the flash EEPROM.
Another technique for preventing over-erasure is to form a split gate on the source side of the floating gate transistor which maintains the cell in enhancement mode even when the floating gate is driven into depletion. The split gate functions in a manner similar to a select transistor in an EEPROM to limit drain-source current during erasure. The split gate is formed by allowing the control gate to overlap the source region of the floating gate transistor. Having a split gate eliminates the problem of over-erasure, but increases the size of the flash EEPROM cell, which limits the number of flash EEPROM cells that can be included in a single flash EEPROM array of a given density. An example of a split gate flash EEPROM cell is described in U.S. Pat. No. 5,130,769, "Nonvolatile Memory Cell", issued to Kuo et al. on Jul. 14, 1992.
A technique which has been used to correct, rather than prevent over-erasure is known as a self-convergence erasing scheme. This scheme is described in an article entitled "A Self-Convergence Erasing Scheme For A Simple Stacked Gate Flash EEPROM", by Yamada et al., IEDM 1991, page 307. The self-convergence technique has two steps, the first step is to bulk erase the array of flash EEPROM cells. After erasure, the second step is to converge the threshold voltages of the cells by injecting some electrons back into the floating gate by using avalanche hot carrier injection. The self-converging operation is accomplished by connecting both the control gate and the source to ground and the drain to a power supply voltage. The threshold voltages converge to a predetermined steady state value that may be adjusted by varying the channel doping. A problem with this technique is that there is a significant drain-source current that may be up to 10 microamps per cell during the self-convergence step. For a very large array size, the total current may be beyond what is practical for an integrated circuit implementation.